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philips semiconductors pca9541 2-to-1 i 2 c master selector with interrupt logic and reset 2004 oct 01 integrated circuits product data sheet supersedes data of 2003 dec 02
philips semiconductors product data sheet pca9541 2-to-1 i 2 c master selector with interrupt logic and reset 2 2004 oct 01 features ? 2-to-1 bi-directional master selector ? i 2 c interface logic; compatible with smbus standards ? pca9541/01 powers-up with channel 0 selected ? pca9541/02 powers-up with channel 0 selected after stop condition detected (bus idle) on channel 0 ? pca9541/03 powers-up with no channel selected and either master can take control of the bus ? active low interrupt input ? 2 active low interrupt outputs ? active low reset input ? 4 address pins allowing up to 16 devices on the i 2 c-bus ? channel selection via i 2 c-bus ? bus initialization/recovery function ? bus traffic sensor ? low rds on switches ? allows voltage level translation between 1.8 v, 2.5 v, 3.3 v and 5 v buses ? no glitch on power-up ? supports hot insertion ? software identical for both masters ? low stand-by current ? operating power supply voltage range of 2.3 v to 5.5 v ? 6.0 v tolerant inputs ? 0 to 400 khz clock frequency ? esd protection exceeds 2000 v hbm per jesd22-a114, 200 v mm per jesd22-a115 and 1000 v cdm per jesd22-c101 ? latch-up testing is done to jesdec standard jesd78 which exceeds 100 ma ? packages offered: so16, tssop16, hvqfn16 applications ? high reliability systems with dual masters ? gatekeeper multiplexer on long single bus ? bus initialization/recovery for slave devices without hardware reset ? allows masters without arbitration logic to share resources description the pca9541 is a 2-to-1 i 2 c master selector designed for high reliability dual master i 2 c applications where system operation is required, even when one master fails or the controller card is removed for maintenance. the two masters (e.g., primary and back-up) are located on separate i 2 c-buses that connect to the same downstream i 2 c-bus slave devices. i 2 c commands are sent by either i 2 c-bus master and are used to select one master at a time. either master at any time can gain control of the slave devices if the other master is disabled or removed from the system. the failed master is isolated from the system and will not affect communication between the on-line master and the slave devices on the downstream i 2 c-bus. three versions are offered for different architectures. pca9541/01 with channel 0 selected at start-up, pca9541/02 with channel 0 selected after start-up and after stop condition is detected, and pca9541/03 with no channel selected after start-up. the interrupt outputs are used to provide an indication of which master has control of the bus. one interrupt input (int_in ) collects downstream information and propagates it to the 2 upstream i 2 c-buses (int0 and int1 ) if enabled. int0 and int1 are also used to let the previous bus master know that it is not in control of the bus anymore and to indicate the completion of the bus recovery/initialization sequence. those interrupts can be disabled and will not generate an interrupt if the masking option is set. a bus recovery/initialization if enabled sends nine clock pulses, a not acknowledge, and a stop condition in order to set the downstream i 2 c-bus devices to an initialized state before actually switching the channel to the selected master. an interrupt is sent to the upstream channel when the recovery/initialization procedure is completed. an internal bus sensor senses the downstream i 2 c traffic and generates an interrupt if a channel switch occurs during a non-idle bus condition. this function is enabled when the pca9541 recovery/initialization is not used. the interrupt signal informs the master that an external i 2 c-bus recovery/initialization needs to be performed. it can be disabled and an interrupt will not be generated. the pass gates of the switches are constructed such that the v dd pin can be used to limit the maximum high voltage, which will be passed by the pca9541. this allows the use of different bus voltages on each pair, so that 1.8 v 2.5 v or 3.3 v devices can communicate with 5 v devices without any additional protection. the pca9541 does not isolate the capacitive loading on either side of the device so the designer must take into account all trace and device capacitances on both sides of the device, and pull-up resistors must be used on all channels. external pull-up resistors pull the bus to the desired voltage level for each channel. all i/o pins are 6.0 v tolerant. an active-low reset input allows the pca9541 to be initialized. pulling the reset pin low resets the i 2 c state machine and configures the device to its default state as does the internal power on reset function.
philips semiconductors product data sheet pca9541 2-to-1 i 2 c master selector with interrupt logic and reset 2004 oct 01 3 ordering information packages temperature range order code topside mark drawing number 16-pin plastic so 40 to +85 c pca9541d/01 pca9541d/01 sot109-1 16-pin plastic tssop 40 to +85 c pca9541pw/01 9541/01 sot403-1 16-pin plastic hvqfn 40 to +85 c pca9541bs/01 41/1 sot629-1 16-pin plastic so 40 to +85 c pca9541d/02 pca9541d/02 sot109-1 16-pin plastic tssop 40 to +85 c pca9541pw/02 9541/02 sot403-1 16-pin plastic hvqfn 40 to +85 c pca9541bs/02 41/2 sot629-1 16-pin plastic so 40 to +85 c pca9541d/03 pca9541d/03 sot109-1 16-pin plastic tssop 40 to +85 c pca9541pw/03 9541/03 sot403-1 16-pin plastic hvqfn 40 to +85 c pca9541bs/03 41/3 sot629-1 standard packing quantities and other packaging data are available at www.standardproducts.philips.com/packaging. pin configuration 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 int0 sda_mst0 scl_mst0 reset scl_mst1 sda_mst1 int1 v ss v dd a3 int_in sda_slave scl_slave a2 a1 a0 sw02008 figure 1. so16/tssop16 pin configuration. 12 11 10 9 5 6 7 8 1 2 3 4 16 15 14 13 sw02034 top view scl_mst0 reset scl_slave a2 a3 sda_slave int1 v ss v dd int0 sda_mst0 scl_mst1 sda_mst1 a0 a1 int_in figure 2. hvqfn16 pin configuration. pin description so/tssop pin number hvqfn pin number symbol function 1 15 int0 active low interrupt output 0 (external pull-up required) 2 16 sda_mst0 serial data master 0 (external pull-up required) 3 1 scl_mst0 serial clock master 0 (external pull-up required) 4 2 reset active low reset input (external pull-up required) 5 3 scl_mst1 serial clock master 1 (external pull-up required) 6 4 sda_mst1 serial data master 1 (external pull-up required) 7 5 int1 active low interrupt output 1 (external pull-up required) 8 6 v ss supply ground 9 7 a0 address input 0 (externally held to gnd or v cc ) 10 8 a1 address input 1 (externally held to gnd or v cc ) 11 9 a2 address input 2 (externally held to gnd or v cc ) 12 10 a3 address input 3 (externally held to gnd or v cc ) 13 11 scl_slave serial clock slave (external pull-up required) 14 12 sda_slave serial data slave (external pull-up required) 15 13 int_in active low interrupt input (external pull-up required) 16 14 v dd supply voltage
philips semiconductors product data sheet pca9541 2-to-1 i 2 c master selector with interrupt logic and reset 2004 oct 01 4 block diagram sw02009 v ss scl_mst1 v dd sda_mst1 power-on reset i 2 c-bus control and register bank a0 int0 interrupt logic int_in reset pca9541 int1 scl_mst0 sda_mst0 input filter slave channel switch control logic a1 a2 scl_slave sda_slave bus sensor bus recovery/ initialization input filter oscillator a3 stop detection stop detection figure 3. block diagram
philips semiconductors product data sheet pca9541 2-to-1 i 2 c master selector with interrupt logic and reset 2004 oct 01 5 device address following a start condition, the upstream master that wants to control the i 2 c-bus or make a status check must send the address of the slave it is accessing. the slave address of the pca9541 is shown in figure 4. to conserve power, no internal pull-up resistors are incorporated on the hardware selectable pins and they must be pulled high or low. a1 a0 a3 a2 sw02011 1 1 1 r/w fixed hardware selectable figure 4. slave address the last bit of the slave address defines the operation to be performed. when set to logic 1 a read is selected while logic 0 selects a write operation. command code following the successful acknowledgement of the slave address, the bus master will send a byte to the pca9541, which will be stored in the command code register. 0 sw02302 0b1 ai 0 0 0 register number b0 auto increment figure 5. command code the 2 lsbs are used as a pointer to determine which register will be accessed. if the auto-increment flag is set (ai=1), the two least significant bits of the command code are automatically incremented after a byte has been read or written. this allows the user to program the registers sequentially or to read them sequentially. during a read operation, the contents of these bits will rollover to a00o after the last allowed register is accessed (a10o). during a write operation, the pca9541 will acknowledge bytes sent to the ie and control registers but will not acknowledge a byte sent to the interrupt status register since it is a read-only register. the 2 lsb's of the command code do not roll over to 00 but stays at 10. only the 2 least significant bits are affected by the ai flag. unused bits must be programmed with zeroes. any command code (write operation) different from a000ai0000o, a000ai0001o, and a000ai0010o will not be acknowledged. at power-up, this register defaults to all zeros. table 1. command code register b1 b0 register name type register function 0 0 ie read/write interrupt enable 0 1 control read/write control switch 1 0 istat read interrupt status 1 1 not allowed each system master controls its own set of registers, however they can also read specific bits from the other system master. pca9541 internal register map ie control istat ie control istat reg#00 reg#01 reg#10 reg#00 reg#01 reg#10 ie 0 control 0 istat 0 master 0 scl_mst0 sda_mst0 master 1 scl_mst1 sda_mst1 sw02072 ie 1 control 1 istat 1 pca9541 0 1 2 3 4 5 6 7 control register detail control 0 control 1 figure 6. internal register map
philips semiconductors product data sheet pca9541 2-to-1 i 2 c master selector with interrupt logic and reset 2004 oct 01 6 interrupt enable and control registers description when a master seeks control of the bus by connecting its i 2 c channel to the pca9541 downstream channel, it has to write to the control register (reg#01) bits mybus and buson allow the master to take control of the bus. the mybus and the nmybus bits determine which master has control of the bus. tables 4 and 5 explain which master gets control of the bus and how. there is no arbitration. any master can take control of the bus when it wants regardless of whether the other master is using it or not. the buson and the nbuson bits determine whether the upstream bus is connected or disconnected to/from the downstream bus. internally, the state machine does the following: if the combination of the buson and the nbuson bits causes the upstream to be disconnected from the downstream bus, then that is done. so in this case, the values of the mybus and the nmybus do not matter. if a master was connected to the downstream bus prior to the disconnect, then an interrupt is sent on the respective interrupt output in an attempt to let that master know that it is no longer connected to the downstream bus. this is indicated by setting the buslost bit in the interrupt status register. if the combination of the buson and the nbuson bits causes a master to be connected to the downstream bus and if there is no change in the buson bits since when the disconnect took effect, then the master requesting the bus is connected to the downstream bus. if it requests a bus initialization sequence, then it is performed. if there is no change in the combination of the buson and the nbuson bits and a new master wants the bus, then the downstream bus is disconnected from the old master that was using it and the new master gets control of it. again, the bus initialization if requested is done. the appropriate interrupt signals are generated. after a master has sent the bus control request: 1. the previous master is disconnected from the i 2 c-bus. an interrupt to the previous master is sent through its int line to let it know that it lost control of the bus. buslost bit in the interrupt status register is set. this interrupt can be masked by setting the buslostmsk bit to 1. 2. a built-in bus initialization/recovery function can take temporary control of the downstream channel to initialize the bus before making the actual switch to the new bus master. this function is activated by setting the businit to 1 by the master during the same write sequence as the one programming mybus and buson bits. when activated and whether the bus was previously idle or not: 9 clock pulses are sent on the scl_slave. sda_slave line is released (high) when the clock pulses are sent to scl_slave. this is equivalent to sending 8 data bits and a not acknowledge finally a stop condition is sent to the downstream slave channel. this sequence will complete any read transaction which was previously in process and the downstream slave configured as a slave-transmitter should release the sda line because the pca9541 did not acknowledge the last byte. 3. when the initialization has been requested and completed, the pca9541 sends an interrupt to the new master through its int line and connects the new master to the downstream channel. businit bit in the interrupt status register is set. the switch operation occurs after the master asking the bus control has sent a stop command. this interrupt can be masked by setting the businitmsk bit to 1. 4. when the bus initialization/recovery function has not been requested (businit=0), the pca9541 connects the new master to the slave downstream channel. the switch operation occurs after the master asking the bus control has sent a stop command. pca9541 sends an interrupt to the new master through its int line if the built-in bus sensor function detects a non-idle condition in the downstream slave channel at the switching time. busok bit in the interrupt status register is set. this means that a stop condition has not been detected in the previous bus communication and that an external bus recovery/initialization must be performed. if an idle condition has been detected at the switching time, no interrupt will be sent. this interrupt can be masked by setting the busokmsk bit to 1. interrupt status can be read. see paragraph interrupt status register description for more information. the mytest and the nmytest bits cause the interrupt pins of the respective masters to be activated for a ofunctional interrupt testo. notes: 1. the regular way to proceed is that a master asks to take the control of the bus by programming mybus and buson bits. nevertheless, the same master can also decide to give up the control of the bus and give it to the other master. this is also done by programming the mybus and buson bits. 2. any writes either to the interrupt enable register or the control register cause the respective register to be updated on the 9th clock cycle, i.e. on the rising edge of the acknowledge clock cycle. 3. the actual switch from one channel to another or the switching off of both the channels happens on a stop command.
philips semiconductors product data sheet pca9541 2-to-1 i 2 c master selector with interrupt logic and reset 2004 oct 01 7 register 0: interrupt enable (ie) register (b1b0 = 00) this register allows a master to read and/or write (if needed) mask options for its own channel. the interrupt enable register described below is identical for both the masters. nevertheless, there are physically 2 internal interrupt enable registers, one for each upstream channel. when master 0 reads/writes in this register, the internal interrupt enable register 0 will be accessed. when master 1 reads/writes in this register, the internal interrupt enable register 1 will be accessed. bit 7 6 5 4 3 2 1 0 symbol 0 0 0 0 buslostmsk busokmsk businitmsk intinmsk table 2. register 0 bit symbol read/ write default description 0 intinmsk r/w 0 0: interrupt on int_in will generate an interrupt on int 0 intinmsk r/w 0 1: interrupt on int_in will not generate an interrupt on int (masked) 1 businitmsk r/w 0 0: after connection is requested and bus initialization requested (businit = 1), an interrupt on int will be generated when the bus initialization is done. note: channel switching is done after bus initialization completed. 1 businitmsk r/w 0 1: after connection is requested and bus initialization requested (businit = 1), an interrupt on int will not be generated when the bus initialization is done (masked). note: channel switching is done after bus initialization completed. 2 busokmsk r/w 0 0: after connection is requested and bus initialization not requested (businit = 0), an interrupt on int will be generated when a non-idle situation has been detected on the downstream slave channel by the bus sensor at the switching moment. note: channel switching is done automatically after the stop command. 2 busokmsk r/w 0 1: after connection is requested and bus initialization not requested (businit = 0), an interrupt on int will not be generated when a non-idle situation has been detected on the downstream slave channel by the bus sensor at the switching moment (masked). note: channel switching is done automatically after the stop command. 3 buslostmsk r/w 0 0: an interrupt on int will be generated after the other master has been been disconnected 3 buslostmsk r/w 0 1: an interrupt on int will not be generated after the other master has been been disconnected. 4 not used r only 0 5 not used r only 0 6 not used r only 0 7 not used r only 0 note: default values are the same for pca9541/01, pca9541/02, and pca9541/03
philips semiconductors product data sheet pca9541 2-to-1 i 2 c master selector with interrupt logic and reset 2004 oct 01 8 register 1: control register (b1b0 = 01) x stands for 0 or 1 and is applied to the master that reads or writes in the control register explained below the control register described below is identical for both the masters. nevertheless, there are physically 2 internal control r egisters, one for each upstream channel. when master 0 reads/writes in this register, the internal control register 0 will be accessed. when master 1 reads/writes in this register, the internal control register 1 will be accessed. bit 7 6 5 4 3 2 1 0 symbol nteston teston 0 businit nbuson buson nmybus mybus table 3. register 1 bit symbol read/ write default description 0 mybus r/w see table 6 mybus bit along with the nmybus bit decides which upstream channel is connected to the downstream channel see table 4 1 nmybus r only see nmybus bit is a copy of the mybus bit for the other channel 1 nmybus r only table 6 see table 4 2 buson r/w see buson bit along with the nbuson bit decides whether any upstream channel is connected to the downstream channel or not 2 buson r/w table 6 connected to the downstream channel or not see table 5 3 nbuson r only see nbuson bit is a copy of the buson bit for the other channel 3 nbuson r only table 6 see table 5 4 businit r/w 0 0: bus initialization not requested 4 businit r/w 0 1 : bus initialization requested 5 not used r only 0 6 teston r/w 0 0: a logic level high to the int line is sent (interrupt cleared) 6 teston r/w 0 1: a logic level low to the int line is sent (interrupt generated) 7 nteston r only 0 0: a logic level high to the int line of the other channel is sent (interrupt cleared) 7 nteston r only 0 1: a logic level low to the int line of the other channel is sent (interrupt generated)
philips semiconductors product data sheet pca9541 2-to-1 i 2 c master selector with interrupt logic and reset 2004 oct 01 9 table 4. mybus and nmybus truth table nmybus mybus slave channel 0 0 to the switching initiator 1 0 to the other channel 0 1 to the other channel 1 1 to the switching initiator table 5. buson and nbuson truth table nbuson buson slave channel 0 0 off 1 0 on 0 1 on 1 1 off notes: 1. switch to the new channel is done when the master initiating the switch request sends a stop command to the pca9541. 2. if master 0 wants to change the connection to the downstream channel in any way, it needs to write to its control register (reg#01), and then send a stop command because an update of the connection to the downstream according to the values in the two internal control registers happens only on a stop command. writing to one control register followed by a stop condition on the other master's ch annel will not cause an update to the downstream connection. 3. when both masters request a switch to their own channel at the same time, the master who last wrote to its control register b efore the pca9541 receives a stop command wins the switching sequence. there is no arbitration performed. 4. auto increment feature (ai=1) allows to program the pca9541 in 4 bytes: start 111a3a2a1a0 + 0 pca9541 address + write 00010000 select reg#00 with ai = 1 data reg#00 interrupt enable register data data reg#01 control register data stop table 6. default control register values bit 7 6 5 4 3 2 1 0 version symbol nteston teston not used businit nbuson buson nmybus mybus pca9541/01 mst_0 0 0 0 0 0 1 0 0 pca9541/01 mst_1 0 0 0 0 1 0 1 0 pca9541/02 mst_0 0 0 0 0 0 0 0 0 pca9541/02 mst_1 0 0 0 0 0 0 1 0 pca9541/03 mst_0 0 0 0 0 0 0 0 0 pca9541/03 mst_1 0 0 0 0 0 0 1 0 pca9541/02 mst_0 0 0 0 0 0 1 0 0 (after stop) mst_1 0 0 0 0 1 0 1 0
philips semiconductors product data sheet pca9541 2-to-1 i 2 c master selector with interrupt logic and reset 2004 oct 01 10 table 7 describes which command needs to be written to the control register when a master device wants to take control of the i 2 c-bus. byte written to the control register is a function of the current i 2 c-bus control status performed after an initial reading of the control register. current status of the i 2 c-bus is determined by the bits mybus, nmybus, buson and nbuson is one of the following: the master reading its control register does not have control and the i 2 c-bus is off. the master reading its control register does not have control and the i 2 c-bus is on. the master reading its control register has control and the i 2 c-bus is off. the master reading its control register has control and the i 2 c-bus is on. `i 2 c-bus off' means that upstream and downstream channels are not connected together. `i 2 c-bus on' means that upstream and downstream channels are connected together. remark: only the 4 lsbs of the control register are described in table 7 since only those bits control the i 2 c-bus control. the logic value for the 4 msbs is specific to the application and are not discussed in the table. the read sequence is performed by the master as following: s e 111xxxx0 e 000x0001 e sr e 111xxxx1 e dataread e p the write sequence is performed by the master as following: s e 111xxxx0 e 000x0001 e datawritten e p table 7. bus control sequence read control register performed by the master write control register performed by the master byte read only the 4 lsbs are shown status nbuson buson nmybus mybus byte written only the 4 lsbs are shown (see note 1) action performed to take mastership hex binary hex 0x0 bus off has control 0 0 0 0 x1x0 0x4 bus on 0x1 bus off no control 0 0 0 1 x1x0 0x4 bus on, take control 0x2 bus off no control 0 0 1 0 x1x1 0x5 bus on, take control 0x3 bus off has control 0 0 1 1 x1x1 0x5 bus on 0x4 bus on has control 0 1 0 0 no write required no change 0x5 bus on no control 0 1 0 1 x1x0 0x4 take control 0x6 bus on no control 0 1 1 0 x1x1 0x5 take control 0x7 bus on has control 0 1 1 1 no write required no change 0x8 bus on has control 1 0 0 0 no write required no change 0x9 bus on no control 1 0 0 1 x0x0 0x0 take control 0xa bus on no control 1 0 1 0 x0x1 0x1 take control 0xb bus on has control 1 0 1 1 no write required no change 0xc bus off has control 1 1 0 0 x0x0 0x0 bus on 0xd bus off no control 1 1 0 1 x0x0 0x0 bus on, take control 0xe bus off no control 1 1 1 0 x0x1 0x1 bus on, take control 0xf bus off has control 1 1 1 1 x0x1 0x1 bus on notes: 1. x0x0 = 0x0, 0x2, 0x8, 0xa x0x1 = 0x1, 0x3, 0x9, 0xb x1x0 = 0x4, 0x6, 0xc, 0xe x1x1 = 0x5, 0x7, 0xd, 0xf
philips semiconductors product data sheet pca9541 2-to-1 i 2 c master selector with interrupt logic and reset 2004 oct 01 11 interrupt status registers description the pca9541 provides 4 different types of interrupt: 1. to indicate to the former i 2 c-bus master that it is not in control of the bus anymore. 2. to indicate to the new i 2 c-bus master that: the bus recovery/initialization has been performed and that the downstream channel connection has been done (built-in bus recovery/initialization active). a abus not well initializedo condition has been detected by the pca9541 when the switch has been done (built-in bus recovery/initialization not active). this information can be used by the new master to initiate its own bus recovery/initialization sequence. 3. indicate to both i 2 c upstream masters that a downstream interrupt has been generated through the int_in pin. 4. functionality wiring test. bus control lost interrupt when an upstream master takes control of the i 2 c-bus while the other channel was using the downstream channel, an interrupt is generated to the master losing control of the bus (int line goes low to let the master know that it lost the control of the bus) immediately after disconnection from the downstream channel. by setting the buslostmsk bit to 1, the interrupt is masked and the upstream master that lost the i 2 c-bus control does not receive an interrupt (int line does not go low). recovery/initialization interrupt before switching to a new upstream channel, an automatic bus recovery/initialization can be performed by the pca9541. this function is requested by setting the businit bit to 1. when the downstream bus has been initialized, an interrupt to the new master is generated (int line goes low). by setting the businitmsk bit to 1, the interrupt is masked and the new master does not receive an interrupt (int line does not go low). when the automatic bus recovery/initialization is not requested, if the built-in bus sensor function (sensing permanently the downstream i 2 c traffic) detects a non-idle condition (previous bus channel connected to the downstream slave channel, was between a start and stop condition), then an interrupt to the new master is sent (int line goes low). this interrupt tells the new master that an external bus recovery/initialization must be performed. by setting the busokmsk bit to 1, the interrupt is masked and the new master does not receive an interrupt (int line does not go low). note: in this particular situation, after the switch to the new master is performed, a read of the interrupt status register is not possible if the switch happened in the middle of a read sequence because the new master does not have control of the sda line downstream interrupt an interrupt can also be generated by a downstream device by asserting the int_in pin low. when int_in is asserted low and if both intinmsk bits are not set to 1 by either master, int0 and int1 both go low. by setting the intinmsk bit to 1 by a master and/or the intinmsk bit to 1 by the other master, the interrupt(s) is (are) masked and the corresponding masked channel(s) does (do) not receive an interrupt (int0 and/or int1 line does (do) not go low). functional test interrupt a master can send an interrupt to itself to test its own int wire or send an interrupt to the other master to test its int line. this is done by: setting the teston bit to 1 to test its own int line. setting the nteston bit to 1 to test the other master int line. setting the teston and/or nteston bits to 0 by a master will clear the interrupt(s). note: interrupt outputs have an open-drain structure. interrupt input does not have any internal pull-up resistor and must not be left floating (e.g., pulled high to v cc through resistor) in order to avoid any undesired interrupt conditions.
philips semiconductors product data sheet pca9541 2-to-1 i 2 c master selector with interrupt logic and reset 2004 oct 01 12 register 2: interrupt status register (b1b0 = 10) the interrupt status register for both the masters is identical and is described below. nevertheless, there are physically 2 in ternal interrupt registers, one for each upstream channel. when master 0 reads this register, the internal interrupt register 0 will be accessed. when master 1 reads this register, the internal interrupt register 1 will be accessed. bit 7 6 5 4 3 2 1 0 symbol nmytest mytest 0 0 buslost busok businit intin table 8. register 2 bit symbol read/ write default description 0 intin r only 0 0: no interrupt on interrupt input (int_in ) 0 intin r only 0 1: interrupt on interrupt input (int_in ) 0: no interrupt generated by the bus recovery/initialization function 1 businit r only 0 1: interrupt generated by the bus recovery/initialization function recovery/initialization done 0: no interrupt generated by bus sensor function 2 busok r only 0 1: interrupt generated by bus sensor function (masked when bus recovery/initialization requested) bus was not idle when the switch occurred 3 buslost r only 0 0: no interrupt generated to the previous master when switching to the new one is initiated 3 buslost r only 0 1: interrupt generated to the previous master when switching to the new one is initiated 4 not used r only 0 5 not used r only 0 6 mytest r only 0 0: no interrupt generated by teston bit f (teston = 0) 6 mytest r only 0 1: interrupt generated by teston bit (teston = 1) 7 nmytest r only 0 0: no interrupt generated due to nteston bit from the other master (nteston = 0 from the other master) 7 nmytest r only 0 1: interrupt generated due to teston bit from the other master (nteston = 1 from the other master) notes: 1. interrupt on a master is cleared after teston bit is cleared the same master or nteston bit is cleared by the other master. 2. if the interrupt condition remains on int_in after the read sequence, another interrupt will be generated (if the interrupt has not been masked) 3. default values are the same for pca9541/01, pca9541/02 and pca9541/03 4. reading the interrupt status register does not clear the mytest, nmytest or the intin bits. they are cleared if: int_in lines goes high for intin bit teston bit is cleared for mytest bit nteston bit is cleared for nmytest bit 5. businit, busok and buslost bits in the interrupt status register gets cleared after a read of the same register is done. prec isely, the register gets cleared on the second clock pulse during the read operation.
philips semiconductors product data sheet pca9541 2-to-1 i 2 c master selector with interrupt logic and reset 2004 oct 01 13 power-on reset when power is applied to v dd , an internal power-on reset holds the pca9541 in a reset condition until v dd has reached v por . at this point, the reset condition is released and the internal registers are initialized to their default states, with: default stop detect pca9541/01 channel 0 pca9541/02 channel 0 pca9541/03 no channel 1. pca9541/01: after power-up and/or insertion of the device in the main i 2 c-bus, the upstream channel 0 and the downstream slave channel are connected together. 2. pca9541/02: after power-up and/or insertion of the device in the main i 2 c-bus, the upstream channel 0 and the downstream slave channel are connected together after a stop condition has been detected by the pca9541/02 on channel 0. if the bus was not idle, channel 0 and the downstream slave device will be connected together as soon as a stop condition occurs at the conclusion of the transmission sequence on channel 0. if the bus was idle, then channel 0 is connected to the downstream slave channel after a stop condition is detected on channel 0. this i 2 c-bus command may or may not be addressed to the pca9541/02. if a switch to channel 1 (initiated by the master on channel 1) is requested (before or after the default switch to channel 0 has been performed), the upstream channel 1 is connected to the downstream slave channel when the master located in channel 1 sends the stop command. 3. pca9541/03: after power-up and/or insertion of the device in the main i 2 c-bus, no channel will be connected to the downstream channel. the device is ready to receive a start condition and its address by a master. if either register writes to its control register, then the connection between the upstream and the downstream channels is determined by the values on the control registers. thereafter, v dd must be lowered below 0.2 v to reset the device. external reset a reset can be accomplished by holding the reset pin low for a minimum of t w . the pca9541 registers and i 2 c state machine will be held in their default states until the reset input is once again high. this input typically requires a pull-up resistor to v dd . default states are: i 2 c upstream channel 0 connected to the i 2 c downstream channel for the pca9541/01 no i 2 c upstream channel connected to the i 2 c downstream channel for the pca9541/02 with channel 0 connected to the downstream i 2 c channel after detection of a stop on the upstream channel. no i 2 c upstream channel connected to the i 2 c downstream channel for the pca9541/03. voltage translation the pass gate transistors of the pca9541 are constructed such that the v dd voltage can be used to limit the maximum voltage that will be passed from one i 2 c-bus to another. 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 v pass vs. v dd 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v pass v dd minimum typical maximum sw00820 2.0 figure 7. v pass voltage figure 7 shows the voltage characteristics of the pass gate transistors (note that the graph was generated using the data specified in the dc characteristics section of this datasheet). in order for the pca9541 to act as a voltage translator, the v pass voltage should be equal to, or lower than the lowest bus voltage. for example, if the main buses were running at 5 v, and the downstream bus was 3.3 v, then v pass should be equal to or below 3.3 v to effectively clamp the downstream bus voltages. looking at figure 7, we see that v pass (max.) will be at 3.3 v when the pca9541 supply voltage is 3.5 v or lower so the pca9541 supply voltage could be set to 3.3 v. pull-up resistors can then be used to bring the bus voltages to their appropriate levels (see figure 16). more information on voltage translation can be found in application note an262 pca954x family of i 2 c/smbus multiplexers and switches.
philips semiconductors product data sheet pca9541 2-to-1 i 2 c master selector with interrupt logic and reset 2004 oct 01 14 characteristics of the i 2 c-bus the i 2 c-bus is for 2-way, 2-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see figure 8). sda scl sw00363 data line stable; data valid change of data allowed figure 8. bit transfer start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line, while the clock is high is defined as the start condition (s). a low-to-high transition of the data line while the clock is high is defined as the stop condition (p) (see figure 9). system configuration a device generating a message is a transmitter: a device receiving is the receiver. the device that controls the message is the master and the devices which are controlled by the master are the slaves (see figure 10). sda scl sw00365 s p sda scl start condition stop condition figure 9. definition of start and stop conditions master transmitter/ receiver slave receiver slave transmitter/ receiver master transmitter master transmitter/ receiver sda scl sw00366 i 2 c multiplexer slave figure 10. system configuration
philips semiconductors product data sheet pca9541 2-to-1 i 2 c master selector with interrupt logic and reset 2004 oct 01 15 acknowledge the number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. eac h byte of eight bits is followed by one acknowledge bit. the acknowledge bit is a high level put on the bus by the transmitter whereas the master ge nerates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges h as to pull down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge r elated clock pulse, set-up and hold times must be taken into account. a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event, the transmitter must leave the data line high to enable the master to generate a stop condition. data output by transmitter scl from master sw00368 data output by receiver 12 89 s start condition clock pulse for acknowledgement acknowledge not acknowledge figure 11. acknowledgement on the i 2 c-bus
philips semiconductors product data sheet pca9541 2-to-1 i c master selector with interrupt logic and reset 2 15 2004 oct 01 0a a a1 a0 slave address start condition r/w 0 sw02306 0 00 00 0 a 1 p a command code register data mask register data control register stop condition acknowledge from slave acknowledge from slave acknowledge from slave auto increment acknowledge from slave s 1 1 1 a3 a2 figure 12. write to the mask and control registers using the auto-increment (ai) bit note: if a 3rd data byte is sent, it will not be acknowledged by the pca9541. sr 0 s0a a 11 1a3a2a1a0 slave address start condition r/w acknowledge from slave acknowledge from slave x command code access to register xx = 00, 01, or 10 1 sw02307 x 00 00 a a p stop condition acknowledge from slave no acknowledge- from master 1 1 1a3a2a1a0 1 1 1a3a2a1a0 1 r/w slave address a a re-start condition auto increment acknowledge from master acknowledge from master xx = 00 : interrupt enable register control register int register xx = 01 : control register int register interrupt enable register xx = 10 : int register interrupt enable register control register figure 13. read the 3 registers using the auto-increment (ai) bit note: if a 4th data byte is read, the first register will be accessed.
philips semiconductors product data sheet pca9541 2-to-1 i c master selector with interrupt logic and reset 2 16 2004 oct 01 s0a a 11 1a3a2a1a0 slave address start condition r/w acknowledge from slave acknowledge from slave 1 command code register 1 sw02308 0 00 00 0 a stop condition acknowledge from slave auto increment data control register ai 0 businit p sda_mst0 p scl_mst0 int1 sda_slave scl_slave int0 after the stop condition, master 1 is disconnected from the downstream channel if the interrupt is not masked (buslostmsk = 0) 1234 56 789 if the interrupt is not masked (businitmsk = 0) master 1 has control of the bus pca9541 has control of the bus master 0 has control of the bus master 0 must wait for the abus free timeo value (between stop and start) defined in the i 2 c specification before sending commands to the downstream devices buson mybus 0 0 00 0 0 figure 14. write to the control register and switch from channel 1 to channel 0 (bus recovery/initialization requested) note: we assume that a read of the control register was done by master 1 and that 000x1010 was read.
philips semiconductors product data sheet pca9541 2-to-1 i c master selector with interrupt logic and reset 2 17 2004 oct 01 s0a a 11 1a3a2a1a0 slave address start condition r/w acknowledge from slave acknowledge from slave 1 command code register sw02309 0 00 00 0 a stop condition acknowledge from slave auto increment data control register ai p sda_mst0 scl_mst0 int1 int0 after the stop condition, master 1 is disconnected from the downstream channel and master 0 is connected to the downstream channel if the interrupt is not masked (buslostmsk = 0) if master 1 was not idle at the switching moment and the interrupt is not masked (busokmsk = 0) master 1 has control of the bus master 0 has control of the bus master 0 must wait for the abus free timeo value (between stop and start) defined in the i 2 c specification before sending commands to the downstream devices 0 0 00 0 00 0 figure 15. write to the control register and switch from channel 1 to channel 0 (bus recovery/initialization not requested)
philips semiconductors product data sheet pca9541 2-to-1 i 2 c demultiplexer with interrupt logic and reset 2004 oct 01 18 typical application pca9541 sd1 sc1 a1 a0 sda_mst0 scl_mst0 reset v dd 3.3 v master 0 sw02010 sda0 scl0 int0 int_in 3.3 v master 1 reset0 int0 sda1 scl1 reset1 int1 a2 sda_mst1 scl_mst1 int1 v ss slave 2 slave 1 slave 3 int v ss v ss v dd v dd sda scl sda scl sda scl slave card a3 figure 16. typical application specific applications the pca9541 is a 2-to-1 i 2 c master selector designed for dual master, high reliability i 2 c applications, where continuous maintenance and control monitoring is required even if one master fails or its controller card is removed for maintenance. the pca9541 can also be used in other applications, such as where masters share the same resource but cannot share the same bus, as a gatekeeper multiplexer in long single bus applications or as a bus initialization/recovery device. high reliability systems in a typical multi-point application, shown in figure 17, the two masters (e.g., primary and back-up) are located on separate i 2 c-buses that connect to multiple downstream i 2 c-bus slave cards/devices via a pca9541/01 for non-hot swap applications or the pca9541/02 for hot swap applications to provide high reliability of the i 2 c-bus. sr02462 scl0 sda0 scl1 sda1 master 1 master 0 pca9541 pca9541 pca9541 pca9541 pca9541 pca9541 pca9541 pca9541 figure 17. high reliability backplane application
philips semiconductors product data sheet pca9541 2-to-1 i 2 c demultiplexer with interrupt logic and reset 2004 oct 01 19 i 2 c commands are sent via the primary or back-up master and either master can take command of the i 2 c-bus. either master at any time can gain control of the slave devices if the other master is disabled or removed from the system. the failed master is isolated from the system and will not affect communication between the on-line master and the slave devices located on the cards. for even higher reliability in multi-point backplane applications, two dedicated masters can be used for every card as shown in figure 18. sr02463 scl0 sda0 scl1 sda1 master 1 master 0 pca9541 scl0 sda0 scl1 sda1 master 1 master 0 pca9541 scl0 sda0 scl1 sda1 master 1 master 0 pca9541 scl0 sda0 scl1 sda1 master 1 master 0 pca9541 figure 18. very high reliability backplane application masters with shared resources some masters may not be multi-master capable or some masters may not work well together and continually lock up the bus. the pca9541 can be used to separate the masters, as shown in figure 19, but still allow shared access to slave devices, such as field replaceable unit (fru) eeproms or temperature sensors. pca9541 slave a0 slave a1 slave a2 master a pca9541 slave b0 slave b1 slave b2 master b main master sw02101 assembly a assembly b sda/scl sda/scl figure 19. masters with shared resources application gatekeeper multiplexer the pca9541/03 can act as a gatekeeper multiplexer in applications where there are multiple i 2 c devices with the same fixed address (e.g., eeproms with address of azo as shown in figure 20) connected in a multi-point arrangement to the same i 2 c-bus. up to 16 hot swappable cards/devices can be multiplexed to the same bus master by using one pca9541/03 per card/device. since each pca9541/03 has its own unique address (e.g., aao, abo, aco, etc), the eeproms can be connected to the master, one at a time, by connecting one pca9541/03 (master 0 position) while keeping the rest of the cards/devices isolated (off position). the alternative, shown with dashed lines, is to use a pca9548 1-to-8 channel switch on the master card and run 8 i 2 c-buses, one to each eeprom card, to multiplex the master to each card. the number of card pins used is the same in either case, but there are 7 less pairs of sda/scl traces on the pc board if the pca9541/03 is used. sw02099 pca9541 pca9541 pca9541 pca9541 pca9541 pca9541 pca9541 pca9541 master 0 pca9548 eeprom eeprom eeprom eeprom eeprom eeprom eeprom eeprom a z b z c z d z e z f z g z h z figure 20. gatekeeper multiplexer application bus initialization/recovery if the i 2 c-bus is hung, i 2 c devices without a hardware reset pin (e.g., slave 1 and 2 in figure 21) can be isolated from the master by the pca9541/03. the pca9541/03 disconnects the bus when it is reset via the hardware reset line, restoring the master's control of the rest of the bus (e.g., slave 0). the bus master can then command the pca9541/03 to send 9 clock pulses/ stop condition to reset the downstream i 2 c devices before they are reconnected to the master or leave the downstream devices isolated. master sw02100 slave 0 slave 1 slave 2 sda/scl sda scl reset slave i 2 c-bus pca9541/03 figure 21. bus initialization/recovery application
philips semiconductors product data sheet pca9541 2-to-1 i 2 c demultiplexer with interrupt logic and reset 2004 oct 01 20 absolute maximum ratings 1, 2 in accordance with the absolute maximum rating system (iec 134). voltages are referenced to gnd (ground = 0 v). symbol parameter conditions rating unit v dd dc supply voltage 0.5 to +7.0 v v i dc input voltage 0.5 to +7.0 v i i dc input current 20 ma i o dc output current 25 ma i dd supply current 100 ma i ss supply current 100 ma p tot total power dissipation 400 mw t stg storage temperature range 60 to +150 c t amb operating ambient temperature 40 to +85 c notes: 1. stresses beyond those listed may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditionso is not implied. exposur e to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. the performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create ju nction temperatures which are detrimental to reliability. the maximum junction temperature of this integrated circuit should not excee d 150 c. dc characteristics v dd = 2.3 v to 3.6 v; v ss = 0 v; t amb = 40 c to +85 c; unless otherwise specified. (see page 21 for v dd = 3.6 v to 5.5 v) symbol parameter test conditions limits unit symbol parameter test conditions min typ max unit supply v dd supply voltage 2.3 e 3.6 v i dd supply current operating mode; v dd = 3.6 v; no load; v i = v dd or v ss ; f scl = 100 khz e 152 200 m a i stb standby current standby mode; v dd = 3.6 v; no load; v i = v dd or v ss ; f scl = 0 khz e 10 100 m a v por power-on reset voltage (note 1) no load; v i = v dd or v ss e 1.5 2.1 v input scl; input/output sda (upstream and downstream channels) v il low-level input voltage 0.5 e 0.3v dd v v ih high-level input voltage 0.7v dd e 6 v i ol low-level out p ut current v ol = 0.4 v 3 e e ma i ol low - level out ut current v ol = 0.6 v 6 e e ma i l leakage current v i = v dd or v ss 1 e +1 m a c i input capacitance v i = v ss e 4 5 pf select inputs a0 to a3 / int_in / reset v il low-level input voltage 0.5 e +0.3v dd v v ih high-level input voltage 0.7v dd e 6 v i li input leakage current v i = v dd or v ss 1 e +1 m a c i input capacitance v i = v ss e 2 3 pf pass gate r on switch resistance v cc = 3.0 v to 3.6 v, v o = 0.4 v, i o = 15 ma 5 14 30 w r on switch resistance v cc = 2.3 v to 2.7 v, v o = 0.4 v, i o = 10 ma 7 17 55 w v swin = v dd = 3.3 v; i swout = 100 m a e 2.2 e v p switch out p ut voltage v swin = v dd = 3.0 v to 3.6 v; i swout = 100 m a 1.6 e 2.8 v v pass switch out ut voltage v swin = v dd = 2.5 v; i swout = 100 m a e 1.5 e v v swin = v dd = 2.3 v to 2.7 v; i swout = 100 m a 1.1 e 2.0 i l leakage current v i = v dd or v ss 1 e +1 m a int0 and int1 outputs i ol low-level output current v ol = 0.4 v 3 e e ma note: 1. v dd must be lowered to 0.2 v in order to reset part.
philips semiconductors product data sheet pca9541 2-to-1 i 2 c demultiplexer with interrupt logic and reset 2004 oct 01 21 dc characteristics v dd = 3.6 v to 5.5 v; v ss = 0 v; t amb = 40 c to +85 c; unless otherwise specified. (see page 20 for v dd = 2.3 v to 3.6 v) symbol parameter test conditions limits unit symbol parameter test conditions min typ max unit supply v dd supply voltage 3.6 e 5.5 v i dd supply current operating mode; v dd = 5.5 v; no load; v i = v dd or v ss ; f scl = 100 khz e 349 600 m a i stb standby current standby mode; v dd = 5.5 v; no load; v i = v dd or v ss ; f scl = 0 khz e 10 200 m a v por power-on reset voltage (note 1) no load; v i = v dd or v ss e 1.5 2.1 v input scl; input/output sda (upstream and downstream channels) v il low-level input voltage 0.5 e 0.3v dd v v ih high-level input voltage 0.7v dd e 6 v i o low level out p ut current v ol = 0.4 v 3 e e ma i ol low - le v el o u tp u t c u rrent v ol = 0.6 v 6 e e ma i il low-level input current v i = v ss 10 e 10 m a i ih high-level input current v i = v dd e e 100 m a c i input capacitance v i = v ss e 4 6 pf select inputs a0 to a3 / int_in / reset v il low-level input voltage 0.5 e +0.3v dd v v ih high-level input voltage 0.7v dd e 6 v i li input leakage current v i = v dd or v ss 1 e +50 m a c i input capacitance v i = v ss e 2 5 pf pass gate r on switch resistance v cc = 4.5 v to 5.5 v; v o = 0.4 v; i o = 15 ma 4 12 24 w v switch out p ut voltage v swin = v dd = 5.0 v; i swout = 100 m a e 3.6 e v v pass s w itch o u tp u t v oltage v swin = v dd = 4.5 to 5.5 v; i swout = 100 m a 2.6 e 4.5 v i l leakage current v i = v dd or v ss 1 e +100 m a int0 and int1 outputs i ol low-level output current v ol = 0.4 v 3 e e ma note: 1. v dd must be lowered to 0.2 v in order to reset part.
philips semiconductors product data sheet pca9541 2-to-1 i 2 c demultiplexer with interrupt logic and reset 2004 oct 01 22 ac characteristics symbol parameter standard-mode i 2 c-bus fast-mode i 2 c-bus unit min max min max t pd propagation delay from sda to sd n or scl to sc n e 0.3 1 e 0.3 1 ns f scl scl clock frequency 0 100 0 400 khz f sclir scl bus initialization/recovery clock frequency 50 150 50 150 khz t buf bus free time between a stop and start condition 4.7 e 1.3 e m s t hd;sta hold time (repeated) start condition after this period, the first clock pulse is generated 4.0 e 0.6 e m s t low low period of the scl clock 4.7 e 1.3 e m s t high high period of the scl clock 4.0 e 0.6 e m s t su;sta set-up time for a repeated start condition 4.7 e 0.6 e m s t su;sto set-up time for stop condition 4.0 e 0.6 e m s t hd;dat data hold time 0 2 3.45 0 2 0.9 m s t su;dat data set-up time 250 e 100 e ns t r rise time of both sda and scl signals e 1000 20 + 0.1c b 3 300 ns t f fall time of both sda and scl signals e 300 20 + 0.1c b 3 300 m s c b capacitive load for each bus line e 400 e 400 m s t sp pulse width of spikes which must be suppressed by the input filter e 50 e 50 ns t vd:datl data valid (hl) 4 e 1 e 1 m s t vd:dath data valid (lh) 4 e 0.6 e 0.6 m s t vd:ack data valid acknowledge e 1 e 1 m s int0 and int1 outputs t iv int_in to int1 or int2 active valid time e 4 e 4 m s t ir int_in to iint1 or int2 inactive delay time e 2 e 2 m s l pwr low level pulse width rejection or int_in input 1 e 1 e ns h pwr high level pulse width rejection or int_in input 0.5 e 0.5 e m s reset t w pulse width low reset 4 e 4 e ns t rst reset time (sda clear) 500 e 500 e ns t rec:sta recovery to start 5, 6 0 e 0 e ns notes: 1. pass gate propagation delay is calculated from the 20 w typical r on and the 15 pf load capacitance. 2. a device must internally provide a hold time of at least 300 ns for the sda signal (referred to the v ih(min) of the scl signal) in order to bridge the undefined region of the falling edge of scl. 3. c b = total capacitance of one bus line in pf. 4. measurements taken with 1 k w pull-up resistor and 50 pf load. 5. resetting the device while actively communicating on the bus may cause glitches or errant stop conditions. 6. upon reset, the full delay will be the sum of t reset and the rc time constant of the sda bus.
philips semiconductors product data sheet pca9541 2-to-1 i 2 c demultiplexer with interrupt logic and reset 2004 oct 01 23 t sp t buf t hd;sta p p s t low t r t hd;dat t f t high t su;dat t su;sta sr t hd;sta t su;sto sda scl su00645 figure 22. definition of timing on the i 2 c-bus handbook, full pagewidth protocol scl sda t hd;sta t su;dat t hd;dat t vd;dat t f r t t buf t su;sta t low t high 1 / f scl t vd;ack sw02278 bit8 (r/w ) acknowledge (a) stop condition (s) start condition (s) bit7 msb (a7) bit6 (a6) t t su;sto figure 23. i 2 c-bus timing diagram; rise and fall times refer to v il and v ih sda scl sw02336 t reset t reset 50% 30% 50% 50% 50% t rec t w reset ledx led off ack or read cycle start figure 24. definition of reset timing
philips semiconductors product data sheet pca9541 2-to-1 i 2 c demultiplexer with interrupt logic and reset 2004 oct 01 24 pulse generator v i v o c l = 50 pf v dd definitions r l = load resistor. c l = load capacitance includes jig and probe capacitance r t = termination resistance should be equal to the output impedance z o of the pulse generators. 6.0 v r t open d.u.t. r l = 500 w sw02279 figure 25. test circuitry for switching times
philips semiconductors product data sheet pca9541 2-to-1 i 2 c demultiplexer with interrupt logic and reset 2004 oct 01 25 so16: plastic small outline package; 16 leads; body width 3.9 mm sot109-1
philips semiconductors product data sheet pca9541 2-to-1 i 2 c demultiplexer with interrupt logic and reset 2004 oct 01 26 tssop16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1
philips semiconductors product data sheet pca9541 2-to-1 i 2 c demultiplexer with interrupt logic and reset 2004 oct 01 27 hvqfn16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 4 x 4 x 0.85 mm sot629-1
philips semiconductors product data sheet pca9541 2-to-1 i 2 c demultiplexer with interrupt logic and reset 2004 oct 01 28 revision history rev date description _2 20041001 product data (9397 750 13629); supersedes data of 02 december 2003 (9397 750 12453). modifications: ? table 7 and its description added to page 10. ? apower-on reseto section on page 13: first sentence: change from a... in a reset state until v dd has reached v por .o to a ... in a reset condition until v dd has reached v por .o add last sentence in section. ? add note 1 to dc characteristics tables on pages 20 and 21, and reference to it at parameter v por . ? ac characterists table on page 22: add note 4 and references to it at parameters t vd;datl and t vd;dath . add notes 5 and 6 and references to them at parameter t rec:sta ? add (new) figure 24, `definition of reset timing'. _1 20031202 product data (9397 750 12453); ecn 853-2436 01-a14594 dated 11 november 2003.
philips semiconductors product data sheet pca9541 2-to-1 i 2 c demultiplexer with interrupt logic and reset 2004 oct 01 29 purchase of philips i 2 c components conveys a license under the philips' i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specifications defined by philips. this specification can be ordered using the code 9398 393 40011. definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed i nformation see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the l imiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any o ther conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affec t device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors ma ke no representation or warranty that such applications will be suitable for the specified use without further testing or modificatio n. disclaimers life support e these products are not designed for use in life support appliances, devices, or systems where malfunction of these products ca n reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applica tions do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes in the productseincluding circuits, standard cells, and/or softwaree described or contained herein in order to improve design and/or performance. when the product is in full production (status `production') , relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for th e use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranti es that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . ? koninklijke philips electronics n.v. 2004 all rights reserved. printed in u.s.a. date of release: 10-04 document number: 9397 750 13629 philips semiconductors data sheet status [1] objective data sheet preliminary data sheet product data sheet product status [2] [3] development qualification production definitions this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the specification in any manner without notice. this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change notification (cpcn). data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level i ii iii

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